Information recording/reproducing method and apparatus using EPRML connection processing system

ABSTRACT

An information recording/reproducing apparatus includes first and second data demodulators having different data discriminating capabilities. The first data demodulator has a lower data discriminating capability and the second data demodulator has a higher data discriminating capability. When the reliability of reliability information for demodulation data generated by the first data demodulator, the second data demodulator is operated so that demodulation data generated by the first data demodulator is replaced by demodulation data generated by the second data demodulator during a period of time when the reliability of the reliability information is deteriorated.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a signal processing system for amagnetic disk device, an optical disk device or the like, and moreparticularly to a signal processing method and apparatus suitable forthe reduction in power consumption of a circuit or LSI.

[0002] Recently, a partial response maximum likelihood (hereinafterabbreviated to PRML) decoding system is put into practice as ahigh-efficiency signal processing system in a magnetic disk device. Thehigh-efficiency signal processing system means a system which canrealize a desired data error rate at a low S/N.

[0003]FIG. 17 shows an example of the construction of a general magneticdisk device using a PRML signal processing system. The original data issupplied to an encoder 7 for error correction code (ECC) through aninterface circuit 8 so that it is added with redundant data necessaryfor error correction. Next, the original data added with redundant datais subjected by a data modulator 6 to modulation necessary for the PRMLsystem and is recorded on a magnetic disk 3 by a magnetic head 4 througha recording/reproducing amplifier 5. A signal reproduced from themagnetic disk is passed through the recording/reproducing amplifier 5and then PRML-processed by a data demodulator 71. The demodulated datais error-corrected by a decoder 2 for error correction code and isthereafter converted through the interface circuit 8 into the originaldata. With such a recording/ reproducing process, the reproduction of alow SIN signal is performed. An extended PRML (EPRML) system, anextended EPRML (EEPRML) system, a TRELLIS demodulation system and soforth are investigated as signal processing systems which make thereproduction of a lower-S/N signal possible.

[0004] On the other hand, the concept of data demodulation withconnection code positioned as a super-ordinate concept of the signalprocessing system has been proposed. A known example includes “ProducingSoft-Decision Information at the Output of a Class-IV Partial ResponseViterbi Detector”, International Conference on Communications '91Conference Record, Volume 2 of 3. This known system is constructed toperform the demodulation of data by combining two signal processingsystems as shown in FIG. 18. First, the data demodulator 71 is used atan initial stage to perform the demodulation of data and the extractionof information which gives the reliability of that data. The result ofdata demodulation at the initial stage is supplied to the next stageformed by the decoder 2 for error correction code which performs thedecoding of data at a high efficiency by utilizing the data reliabilityinformation. Thus, a connection code scheme utilizing the datareliability information with the coupling thereof with the errorcorrection code decoding system being hitherto taken into considerationis investigated as an effective system for realizing the high-efficiencysignal processing system.

[0005] In the signal processing system suitable for the implementationof high efficiency and the data demodulating system using the connectioncode, as mentioned above, high-efficiency data demodulation is attainedbut an operation processing for performing data demodulation isexponentially complicated. In general, a signal processing circuithaving a low data discriminating capability (for example, the PRMLsystem) is simple in data discriminating method and small in bothcircuit scale and power consumption whereas a signal processing circuithaving a high data discriminating capability (for example, the EPRMLsystem or the TRELLIS system) is complicated in circuit and large inpower consumption. Accordingly, a signal processing LSI for performingthe data demodulation of a low-S/N signal has an increase in scale of anoperating circuit and an increase in power consumption thereof. Theincrease in power consumption results in a substantial hindrance to therealization of a signal processing LSI.

SUMMARY OF THE INVENTION

[0006] An object of the present invention is to realize a datademodulating system suppressing an increase in power consumption whichresults in the largest hindrance to the LSI implementation of ahigh-efficiency signal processing system. More particularly, an objectof the present invention is to realize a data demodulating method andsystem which can operate a high-efficiency signal processing system suchas an EPRML system, a TRELLIS system or the like with a powerconsumption approximately equivalent to that in the PRML system.

[0007] In the present invention, the barometer of a data reliabilityproposed by a connection code scheme is utilized in respect to thereduction of a power consumption, thereby making it possible toremarkably reduce the power consumption of a signal processing circuitwith a high-efficiency decoding performance being kept. Basically, thisis realized by combining a first signal processing circuit having alower data discriminating capability and a second signal processingcircuit having a higher data discriminating capability, providing areliability detecting circuit for extracting a data reliability at thetime of data discrimination by the first signal processing circuit, andoperating the second signal processing circuit adaptively in accordancewith the extracted reliability.

[0008] In a data discriminating process of the present invention, thefirst signal processing circuit having a lower data discriminatingcapability is operated while the second signal processing circuit havinga higher data discriminating capability is operated, as required. Thereliability detecting circuit detects the deterioration in reliabilityof data discrimination by the first signal processing circuit and thesecond signal processing circuit starts and completes its datadiscriminating operation on the basis of the result of detection by thereliability detecting circuit.

[0009] In the present invention, the second signal processing circuitdemodulates data for which the data discriminating performance of thefirst signal processing circuit is insufficient. Therefore, the overalldata reproducing performance is approximately represented by the datadiscriminating performance of the second signal processing circuit.Regarding a power consumption, on the other hand, the operating periodof the second signal processing circuit having a large power consumptionis limited to only a required time. Therefore, the power consumption ofthe overall data demodulator is approximately determined by the firstsignal processing circuit.

[0010] The above object of the present invention is achieved by the datademodulating system mentioned above.

[0011] According to the present invention, a remarkable reduction inpower consumption of a signal processing circuit with a high-efficiencydecoding performance kept is made possible by effectively utilizing thebarometer of a data reliability proposed by a connection code scheme.

[0012] A specific effect will be estimated in regard to a datademodulating system in which a switching is made between a PRML systemand an EPRML system. In the case where a code error rate is about 10⁻⁴which may be regarded as the lower limit of a code error rate usuallyallowed in a magnetic disk device, the rate of a likelihood differenceΔnk falling within this setting range comes to about 10⁻³. Namely, theactivation of EPRML only one time for 1000 bits suffices. When an EPRMLprocessing circuit is activated once, the processing is performed for aperiod of about 50 bits. The operation rate of the EPRML processingcircuit results in about {fraction (1/100)} and a power consumption iscorrespondingly reduced.

[0013] As compared with the PRML system, the EPRML system has anestimated improvement of S/N equal to or greater than about 2 dB in thecase where the ratio of the half band width of the reversal ofregenerative isolated magnetization of a magnetic recording device tothe half band width of a record signal is about 2.5 falling within arange in which the device is put into practice. Accordingly, when theabove processing is performed, the effect of improvement of S/N equal toor greater than 2 dB as compared with the PRML system approximatelyequivalent to a decoding system based on the EPRML system can beachieved with a power consumption which is approximately equal to thatin the PRML system.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a block diagram showing an embodiment of a datademodulating circuit of the present invention;

[0015]FIGS. 2A and 2B show PRML and EPRML trellis diagrams;

[0016]FIG. 3 shows the details of the PRML trellis diagram;

[0017]FIGS. 4A and 4B show examples of detection of data reliabilityinformation;

[0018]FIG. 5 shows the classification of data reliability informationdetecting equations;

[0019]FIG. 6 shows a reliability detection range for the distribution ofPRML likelihood differences in the present invention;

[0020]FIGS. 7A and 7B show examples of transition in the PRML trellisdiagram;

[0021]FIG. 8 is a timing chart of the data demodulating circuit of thepresent invention;

[0022]FIG. 9 shows an example of the construction of a data reliabilitydetecting circuit in PRML;

[0023]FIG. 10 is a timing chart of the operation of the data reliabilitydetecting circuit shown in FIG. 9;

[0024]FIG. 11 shows an example of the construction of another datareliability detecting circuit in PRML;

[0025]FIG. 12 shows an example of the construction of an EPRMLprocessing circuit;

[0026]FIG. 13 is a block diagram showing another embodiment of the datademodulating circuit of the present invention;

[0027]FIG. 14 shows an example of another construction which embodiesthe present invention;

[0028]FIG. 15 shows an example of a further construction which embodiesthe present invention;

[0029]FIG. 16 shows an embodiment of a magnetic recording/reproducingapparatus using the present invention;

[0030]FIG. 17 is a diagram showing the concept of a data demodulatingmethod in a general magnetic disk device or the like; and

[0031]FIG. 18 is a diagram showing the concept of a data demodulatingmethod using a connection code.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] A data demodulating system based on the splice or combination ofa PRML system and an EPRML system, as an embodiment of the presentinvention, will now be described in detail with data of a 8/9GCR (GroupCoded Recording) (0, 4/4) code taken as an example.

[0033] Before showing the details of a data demodulating circuit, theprinciple of operation of each of the PRML and EPRML systems and amethod for extracting data reliability information will be described indetail. As well known, the operation of each of a PRML signal processingsystem and an EPRML signal processing system can be explained using atrellis diagram. FIGS. 2A and 2B show the trellis diagrams of both thesystems. In the figure, reference symbol ak represents an input signalto PRML or EPRML at an instant of time k. Herein, reference numeral 32denotes a state and numeral 31 denotes a state transition. The upper andlower sides of a label (ak/rk) indicate input and output signal values,respectively.

[0034] A state of each signal processing system is determined by theprevious input signal series. In the case of the PRML system, thepresent signal level is influenced by only an input signal ak-2preceding the present signal by two time slots. Therefore, the number ofstates S is 2. Provided that a state at time k is represented by Sik,the state Sik is represented by Sik= (ak-2 |ak(1, 0)). In the case ofthe EPRML system, the present signal level is influenced by the previoussignals extending three time slots. Therefore, a state at time k isrepresented by Sik ((ak-3, ak-2, ak-1) ak(1, 0)) and the number ofstates is 8.

[0035] The basic operation of the PRML system will be described. Statetransitions originating from a plurality of states at time k-2 convergesinto a certain specified state at time k. For these state transitions,the second power of a difference between an output signal indicated inthe lower side of each label and an input signal is called a branchmetric. Also, the accumulated value of branch metrics for each state upto the present instant of time is called a path metric. Only that statetransition among state transitions converging into the certain specifiedstate at the instant of time k in which the sum of a path metric up totime k-2 and a branch metric corresponding to each state transitiontakes the smallest value, is selected as a state transition (or path)which satisfies the maximum likelihood (or highest probability)condition.

[0036] The above process is divided into the following steps. Namely, apath metric and a branch metric are added (Add). Next, the values ofaddition for respective states are compared (Compare) to select a statetransition which provides the minimum value (Select). This series ofoperations is abbreviated to ACS. The maximum likelihood decoding is amethod in which the ACS operation is repeated for each instant of timeand each state so that data is decided at a point of time when pathsultimately converges into one on the trellis diagram.

[0037] An example of ACS for PRML will be described in detail by use ofFIG. 3. A path metric and a branch metric at time k are denoted byPMn(k) and BMnm(k), respectively. The suffix represents a state. PMn(k)is given by the following equations:

PM1(k)=min{PM1(k-2)+BM11(k), PM0(k-2)+ BM01 (k)}  . . . (1)

PM0(k)=min{PM1(k-2)+BM10(k), PM0(k-2)+ BM00(k)}  . . . (2)

[0038] where a min () function gives the minimum value in an argument.

[0039] Such an operation is repeated and an ultimately surviving path(or survival path) gives the maximum likelihood data.

[0040] Though the EPRML system has the number of states (or 8) increasedas compared with that (or 2) in the PRML system, the basic operation anddata demodulating method for EPRML system are the same as those for PRMLsystem.

[0041] Next, description will be made of a method for extraction of datareliability information which is a key subject of the present invention.At any instant of time k, the reliability RLB(k) of a selected path isobtained in accordance with a procedure which will be mentionedhereinbelow. The reliability herein referred to indicates the degree ofmatching of decided data with the original data. For the convenience ofexplanation, the manner of determination of the reliability RLB(k) willbe described in detail by use of trellis diagrams for PRML system shownin FIGS. 4A and 4B by way of example.

[0042] A difference signal of each state transition at each instant oftime and each state (that is, likelihood difference signal) is definedby

Δ1(k)=abs{PM1(k-2)+BM11(k)}−{PM0(k-2)+ BM01(k)}  . . . (3)

Δ0(k)=abs{PM1(k-2)+BM10(k)}−{PM0(k-2)+ BM00(k)}  . . . (4)

[0043] where an abso function gives the absolute value of an argumentand the value of k in the parenthesis () represents an instant of time.

[0044] In FIG. 4A, it is assumed that a state transition from a state 1is generated at time k0 and a state transition from a state “0” isgenerated at time k12. In this case, it should be noted that alikelihood function corresponding to a new state transition starts fromtime k4. Likelihood functions at times k0 and k2 are calculated frompath branches before time k0.

[0045] Δ1(k4 ) at time k4 is determined from a metric difference of asignal through a path of S{k0, k2, k4} {1, 1, 1} or S{k0, k2, k4}={1, 0,1}. Also, Δ0(k4 ) is determined from a metric difference of a signalthrough a path of S{k0, k2, k4}={1, 1, 0} or S{k0, k2, k4 }={1, 0, 0}.Similarly, Δ1(k14) is determined from a metric difference of a signalthrough a path of S{k0, k2, k4, . . . k14}={1, 1, . . . , 1, 1} or S{k0,k2, k4, . . . , k14} ={1, 0, . . . , 0, 1}. Δ0(k14) is determined from ametric difference of a signal through a path of S{k0, k2, k4, . . . ,k14}={1, 1, . . . , 1, 0} or S{k0, k2, k4, . . . , k14} ={1, 0, . . .,0, 0}. In the shown example, since a branch from a state “0” isselected at time k12, Δ0(k2 ), . . . , Δ0(k12) are selected asdifference signals. In the figure, it is assumed that the dotted line isnot selected.

[0046] In FIG. 4B, it is assumed that a state transition from a state“1” is generated at time k0 and a state transition is generated for areceive signal at time k2 immediately after time k0. In this case, too,the likelihood function is similarly determined. Namely, Δ1(k4 ) at timek4 is determined from a metric difference of a signal through a path ofS{k0, k2, k4}={1, 1, 1} or S{k0, k2, k4}={1, 0, 1}. Also, Δ0(k4 ) isdetermined from a metric difference of a signal through a path of S{k0,k2, k4}={1, 1, 0} or S{k0, k2, k4}={1, 0, 0}.

[0047] In FIG. 5, operational equations giving those likelihooddifferences An(k) are classified. In the PRML signal processing system,since each of a start end and a terminal end involves two states, fourcombinations in total are yielded. A likelihood function immediatelyafter a path branch, that is, in an initial state is given by thefollowing equation:

PL(k0)=1/{2{1+exp(Δn(k0)}}   . . . (5)

[0048] With this taken as the initial state, a reliability RLB(k) eachtime a receive signal is inputted to the PRML signal processing circuitis given by such a repetitive form as shown by the following equation:

PLB(kn)={1−PL(kn-2)} PL(kn)+PL(kn-2) {1−PL(kn)}.   . . . (6)

[0049] It is meant that as the value of PLB(k) is smaller, thepossibility of selection of a correct path is higher. When thereliability is deteriorated, the value of RLB(k) approaches a limitvalue ½. It is understood from equation (6) that RLB(k) is substantiallydetermined by a larger value of PL(k). Also, it is understood fromequation (5) that PL(k) is determined by Δn(k). Accordingly, datareliability information, that is, the reliability of selection of acorrect path on the trellis diagram is approximately determined by theminimum value of Δn(k). Namely, it is meant that as two path metricdifferences are closer to each other, the reliability of a selected pathis lower.

[0050] On the basis of the above-mentioned data reliability information,a data reliability information detecting circuit 24 shown in FIG. 1performs an operation based on the values of two path metric differencesΔn(k) shown by equations (3) and (4).

[0051] First, reference will be made to the range of distribution ofΔn(k). In the case where a receive signal through arecording/reproducing path is affected by noises, the receive signaltakes any value of (1, −1, 0) as shown by the trellis diagram shown inFIG. 2A and the polarity of a receive signal rk at the time of statechange is determined. Therefore, the value of Δn(k) comes to 1 or 0 fromdecision equations shown in FIG. 5.

[0052] On the other hand, in the case where Gaussian noises aresuperimposed in the recording/reproducing path, a receive signal (ri,rk) assumes a Gaussian distribution centering around {1, 0, −1} andhence the value of Δn(k) takes a Gaussian distribution centering around1 or 0.

[0053] A schematic diagram of the distribution of Δn(k) is shown in FIG.6. In the figure, Δ0 represents a likelihood difference of a state “0”and Δ1 represents a likelihood difference of a state “1”. The showndistribution means that in the case where Δn(k) to be 0 in itselfbecomes larger than 0.5 due to the influence of noises, a decision erroroccurs in the PRML process. On the other hand, in the case where Δn(k)to be 1 in itself becomes smaller than 0.5 due to the influence ofnoises, there similarly results in that a decision error occurs in thePRML process. Accordingly, a data portion distributed in the vicinity ofΔn(k)=0.5 has a higher decoding error and the rate of occurrence of adecoding error is exponentially decreased as Δn(k) gets near 1 or 0.Thus, a threshold having a certain range centering around Δn(k)=0.5 canbe set so that the reliability of data is regarded as being low in thecase where the value of Δn(k) falls within the threshold setting range.Namely, data included in the setting range has a high possibility thatit involves a code error. However, it should be noted that data includedin the setting range has not only erroneous data with code error butalso correct data in itself and the amount of correct data is largerthan that of erroneous data.

[0054] Though the above-mentioned data reliability extracting method hasbeen shown in conjunction with the PRML system, it is needless to saythat the same holds for another signal processing system.

[0055] Other methods will be shown as barometers which give the datareliability. First, there will be shown a method for giving the datareliability by detecting the unconvergence of survival paths.

[0056] In general, the original data is coded in order to convergesurvival paths of a data demodulating circuit in a fixed period of time.The explanation will be made in conjunction with an example in which thecoding is made in the 8/9GCR (0, m/h) (m=4, h=4) shown in the presentembodiment. “GCR” is an abbreviation of Group Coded Recording. Here, mrepresents the maximum number (or run length) of continuous bits of 1 or0 after encoding and h represents the maximum number of continuous 1'sor 0's when bits after encoding are seen every two bits.

[0057] The states of survival paths in the PRML system using the (0,4/4) code are shown in FIGS. 7A and 7B. In the case where the S/N of areceive signal is satisfactory, survival paths on the trellis diagramconverge into one path one time at intervals of 11 bits at the maximum(k0 to k10) by an interleaving process in which the operation isperformed every three bits of receive data, as shown in FIG. 7A.Therefore, the path memory length of the PRML demodulating circuit islimited to 10 bits. (Since the operation is performed in an interleavedmanner, the path memory length of each PRML demodulating circuit is 5bits.)

[0058] On the other hand, consider the case where a state transition asshown in FIG. 7B is assumed at time k12 due to noises so that an erroris generated as for demodulation data. Since the state transition attime k12 is not generated, the path memory length is short at and aftertime k14. Though any data is erroneous as for demodulation data, it isshown that a data reliability can also be realized by detecting theunconvergence of survival paths as the data reliability. Such a datareliability detecting method makes it possible to generate a datareliability quickly as compared with the above-mentioned method usingpath metric differences.

[0059] For example, in the above-mentioned method using path metricdifferences, a demodulation error in the maximum bit period of times k0to k2 1 having two settled trellis transitions at opposite ends in the(0, 4/4) code is detected at time k22. On the other hand, in the methodusing the path memory length, the demodulation error is detectable attime k14. As a result, it is possible to reduce the circuit scale ofdelay circuits 23 and 27 (which will be mentioned later on) and toshorten the delay of processing for demodulation data.

[0060] Next, a method of detecting data having no matching with a codingrule will be shown as another barometer for giving the data reliabilitywill be shown. In the 8/9GCR code, 9-bit data is assigned to 8-bit inputdata. Though a bit series of 9 bits includes 512 kinds of representablecombinations, 256 kinds matching with the coding rule are selected fromamong the 512 kinds to perform the encoding. On the other hand, in adecoder for decoding data, 9-bit data demodulated by a data demodulatingcircuit is converted into 8-bit decode data. The detection of theerroneousness of data demodulated by the data demodulating circuit iseffected by detecting the absence of the demodulation data of the datademodulating circuit in the 9-bit data series determined by the encoderfor the 8-bit input data. Thus, an abnormality in data series at thetime of encoding can also be given as a data reliability.

[0061] The plurality of barometers for data reliability as mentionedabove may be operated independently or in combination.

[0062] An embodiment of a data demodulating circuit using theabove-mentioned data reliability is shown in FIG. 1. A receive signal ofthe data demodulating circuit includes the addition of transmit data (ororiginal data) transmitted from a host computer (not shown) and noisesmixed as the result of the passing through a recording/reproducing pathof a magnetic disk, a reproducing amplifier or the like. In the datademodulating circuit, this receive signal is divided into two series oneof which is supplied to a PRML processing circuit 22 and the other ofwhich is supplied to an EPRML processing circuit 26 through the delaycircuit 23 which has a proper length or delay and a (1+D) circuit 25which performs signal conversion.

[0063] The delay circuit 23 is provided for absorbing a data delaycaused by the PRML processing circuit 22 and a detection delay of thedata reliability information detecting circuit 24. The detection delayof the data reliability information detecting circuit 24 corresponds tothat time delay depending upon the receive signal which is causedbecause the reliability of a selected path is provided at an instant oftime when the above-mentioned data reliability information convergesinto one survival path. For example, in the case of FIG. 4A, a datareliability from time k0 to time k12 is obtained at time k14. Therefore,it is necessary for the delay circuit 23 to absorb the detection delayof the data reliability information detecting circuit 24.

[0064] Since the receive signal inputted to the data demodulatingcircuit is a signal for PRML system, the (1+D) circuit 25 converts thereceive signal of the PRML system into a receive signal for EPRMLsystem.

[0065] The data reliability information detecting circuit 24 obtainsdesired data for reliability decision by use of a part of theabove-mentioned likelihood decision information of the PRML processingcircuit 22 to generate a switching control signal SW and an EPRMLprocessing circuit activation signal EPRON.

[0066] The delay circuit 27 is provided for correcting a deviation intiming of demodulation data between the EPRML processing circuit 26 andthe PRML processing circuit 22 which is caused by a data demodulationtime of the EPRML processing circuit 26 and so forth.

[0067] A multiplexer 28 makes a switching between an output of the delaycircuit 27 and demodulation data of the EPRML processing circuit 26 inaccordance with the switching control signal SW.

[0068] The EPRML processing circuit activation signal EPRON is issued,for example, in the case where the reliability of data demodulated bythe PRML processing circuit 22 is deteriorated.

[0069] The switching control signal SW is generated in a period of timewhen the data reliability of the PRML processing circuit 22 is low ordata has a high possibility of occurrence of a discrimination error. Thesignal SW performs the replacement of demodulation data of the PRMLprocessing circuit 22 in such a period by demodulation data of the EPRMLprocessing circuit 26.

[0070] The period for the replacement of demodulation data of the PRMLsystem by demodulation data of the EPRML system will be explained byvirtue of FIGS. 7A and 7B. For the explanation of the demodulation datareplacement period, it is necessary to explain the coding of theoriginal data. As mentioned above, in the PRML system using the (0, 4/4)code, survival paths on the trellis diagram converges into one path onetime at intervals of 11 bits at the maximum (k0 to k10), as shown inFIG. 7A.

[0071] Now consider the case where a state transition at time klO is notgenerated, as shown in FIG. 7B. In this case, decode data in the maximumbit period of times k0 to k21 having two settled trellis transitions atopposite ends is erroneously demodulated. At the same time, the state ofa metric difference Δn(k) or the suffix n is settled to “0” or “1” attime k20 so that the decision of a data reliability becomes possible.Accordingly, the replacement by demodulation data of the EPRML systemactivated by one data reliability deterioration can be performed withdemodulation data of the PRML system in the 21-bit period being made anobject of replacement.

[0072] Generally, in the case where a (0, m/h) code is used, data of4(h+1)+1 points may be replaced by EPRML data from a similar point ofview. As mentioned in the foregoing, it is required that a section ofdata to be replaced by demodulation data of the EPRML system should beselected corresponding to the coding. Also, it is needless to say thatthe present detecting system is effective even in the case where aplurality of errors in trellis transition occur in the above-mentionedperiod.

[0073] The operation of the above data decoder will be explained by useof a time chart shown in FIG. 8. When a receive signal is applied to aninput of the PRML processing circuit 22 at an instant of time indicatedby A in FIG. 8, output data delayed by the length of the path memory ofthe PRML processing circuit 22 is obtained at an instant of time B. AnEPRML processing circuit activation signal EPRON as an output of thedata reliability information detecting circuit 24 is generated at atiming of an instant of time C even with the maximum delay. A delayamount for an input signal of the EPRML processing circuit 26 to beprovided by the delay circuit 23 is determined by a used conversioncode, as mentioned earlier. In the (0, 4/4) code, the delay of 22 bitsis necessary. Accordingly, a point indicated by the instant of time C inFIG. 8 is an instant of time of signal input to the EPRML processingcircuit 26. Further, output data of the EPRML processing circuit 26 isdelayed by the length of a path memory thereof and is outputted at aninstant of time D. Output data of the PRML processing circuit 22 issubjected by the delay circuit 27 to timing adjustment for the outputdata of the EPRML processing circuit 26 obtained at the instant of timeD. A switching control signal SW as an output of the data reliabilityinformation detecting circuit 24 takes a turned-on condition during theabove-mentioned data replacement period so that PRML demodulation datais replaced by EPRML demodulation data.

[0074] Numeric values such as specific delay times mentioned above aregiven by way of example. If the coding method differs, a change toproper numeric values is necessary. Also, the timing adjustment isnecessary depending upon the delays of the PRML and EPRML circuits(including the delay of a pipe-line processing) or a different datareliability detecting method. According to circumstances, the timing ofgeneration of the EPRML processing circuit activation signal EPRON orthe switching control signal SW is different. Therefore, it is needlessto say that the circuit should be constructed taking those timings intoconsideration.

[0075] Next, embodiments of main constituent elements including the PRMLprocessing circuit, the EPRML processing circuit and the datareliability information detecting circuit will be shown hereinbelow.

[0076] One embodiment of the PRML processing circuit 22 and the datareliability information detecting circuit 24 is shown in FIG. 9. Thefollowing description will be made assuming that a data reliability inthe present embodiment is given by use of the likelihood differences oftwo states of the PRML processing circuit and the indication of a pathmemory length as being larger than a predetermined value. The PRMLprocessing circuit 22 is basically composed of a branch metric operatingcircuit 13, an adder circuit 14 and a compare and select circuit 15. Thebranch metric operating circuit 13 generates numeric values BM11(k),BM01(k), BM00(k) and BM10(k) corresponding to four branches shown inFIG. 3. The compare and select circuit 15.1 and 15.2 perform an ACSoperation for data demodulation. Namely, path metrics PM1(k-1) andPM0(k-1) and branch metrics BM11(k), BM01(k), BM00(k) and BM10(k) areadded by the adder circuit 14, the comparison in magnitude between theresults of addition is made, and path metrics PM1(k) and PM0(k) newlyupdated in accordance with the results of selection are outputted. Apath memory 19 determines a survival path from signals obtained throughthe processing of the outputs of the compare and select circuit 15.1 and15.2 by a state change detecting circuit 16 to generate demodulationdata.

[0077] The data reliability information detecting circuit 24 gives thereliability of demodulation data by virtue of a reliability which isformed by the compare and select circuits 15.3 and 15.4, settingcircuits 18.1 and 18.2, the state change detecting circuit 16 and amultiplexer 17.1 and uses the likelihood differences of two states and areliability which is formed by a path memory overflow detecting circuit20 and indicates that the path memory length is larger than thepredetermined value. The compare and select circuits 15.3 and 15.4 areused for judging whether or not the two likelihood differences fallwithin a threshold indicated by a register 21, and the likelihooddifferences of two states are outputted as a first reliability by thesetting circuits 18.1 and 18.2, the state change detecting circuit 16and the multiplexer 17.1.

[0078] The path memory overflow detecting circuit 20 counts an intervalfrom the generation of a state transition to the reconvergence ofsurvival paths so that an overflow pulse OVF is generated and outputtedas a second reliability in the case where the count value exceeds apredetermined constant value (5 in the present embodiment).

[0079] The EPRML activation signal EPRON is generated as a signalproduced by a logical sum of the overflow pulse OVF and an output of themultiplexer 17.1 and serves as a signal for activating the EPRMLprocessing circuit. The switching control signal SW is a control signalof a fixed period generated by a switching control signal generatingcircuit 17.3 which is triggered by a version of the EPRML activationsignal EPRON delayed in a delay circuit 17.2 by a data demodulation timeof the EPRML processing circuit 26. The value of the register 21 isfreely set from the exterior by a microcomputer.

[0080] The timing of operation of the PRML processing circuit 22 and thedata reliability information detecting circuit 24 of FIG. 9 mentionedabove will be described in detail by use of FIG. 10. A waveform shown in(a) of FIG. 10 represents an input signal to the PRML processing circuit22. The receive signal of the PRML processing circuit assumes a waveformincluding three values of (+1, 0, −1), as shown in (a) of FIG. 10. Thiswaveform shows an example in which a signal amplitude at time 9 toindicate the polarity of +1 in itself is deteriorated due to theinfluence of noises or the like whereas a signal amplitude at time 6rises to a positive polarity. In the case where the results of judgementby the compare and select circuits 15.3 and 15.4 for likelihooddifferences exist in the threshold setting range, a signal indicatingthe deterioration of the reliability is generated as a firstreliability, as shown in (b) and (c) of FIG. 10. These signals cause thesetting circuits 18.1 and 18.2 to generate setting signals as shown in(d) and (c) of FIG. 10. Further, when a path is settled by the statechange detecting circuit 16 (see (f) of FIG. 10), the output signals ofthe setting circuits 18.1 and 18.2 are latched in accordance with thestate of the path so that an EPRML activation signal as shown at time 15in (g) of FIG. 10 is generated if the latched signal has a high level. Aswitching control signal SW (not shown) is generated for a fixed periodof time on the basis of the EPRML activation signal, as shown in theforegoing.

[0081] On the other hand, in the case where a signal amplitude of +1 attime 21 is deteriorated due to the influence of noises or the like, asshown in FIG. 10, an overflow pulse OVF is generated and outputted as asignal representative of a second reliability at time 21, that is, at aninstant of time when a path memory length of the PRML (for example, fivesamples) is exceeded from a state transition generated at time 15. Likethe reliability information using the likelihood differences, theoverflow pulse OVF is outputted as an EPRML activation signal EPRONwhich in turn generates a switching control signal SW for a fixed periodof time.

[0082]FIG. 11 shows another embodiment of the PRML processing circuit 22and the data reliability information detecting circuit 24. The presentembodiment corresponds to an example of the construction in the casewhere the PRML processing circuit 22 is simplified as compared with thatshown in FIG. 9. Like the case of FIG. 9, it is assumed that a datareliability is given by use of the likelihood differences of two statesof the PRML processing circuit and information indicating that a pathmemory length is larger than a predetermined value. The construction ofthe PRML processing circuit 22 is simpler than that shown in FIG. 9 butthe basic operation thereof is the same. A memory circuit 50 stores areceive signal in the case where a reset signal is generated. The memorycircuit 50 corresponds to a path metric value. operating circuits 51, 52and 53 perform the addition of the path metric value and a branch metricvalue and the generation of a likelihood difference at each state.Comparators 54 and 55 perform a path selection based on the likelihooddifference and generate a reset signal to a path memory counter 56 andso forth and a set signal to a path memory 19. The data reliabilityinformation detecting circuit 24 receives the results of operation bythe operators 52 and 53 as basic information of likelihood differencesfrom the PRML processing circuit 22 to obtain information of a datareliability. The likelihood difference of each state is obtained byselecting the results of operation of the operators 52 and 53 by use ofmultiplexers 57 on the basis of sel signals. Thereafter, an operationprocessing based on equations (3) and (4) is performed by absolute valuecircuits 58 and comparator circuits 59. The comparator circuit 59compares a numeric value of a register 21 and the likelihood differencesof two states to generate a signal which is turned on when a conditionis satisfied. Setting circuits 60 detect the likelihood differences oftwo states in a detection period from the generation of a path branch.Multiplexers 61 selects which of the likelihood differences of twostates should be outputted as a reliability. As a result, a firstreliability for an EPRML activation signal is generated.

[0083] On the other hand, a path memory overflow detecting circuit 20 isa circuit for judging whether or not the path memory counter 56 is overa path memory length. In the case where the path memory counter 56 isover 5, the path memory overflow detecting circuit 20 generates anoverflow pulse OVF to obtain a second reliability. As in the foregoingembodiment, the EPRML activation signal EPRON is a signal produced by alogical sum of the overflow pulse OVF and an output of the multiplexer61 and serves as an activation signal for the EPRML processing circuit.A switching control signal SW is a control signal generated in a fixedperiod of time by a switching control signal generating circuit 17.3which is triggered by a version of the EPRML activation signal EPRONdelayed in a delay circuit 17.2 by a data demodulating time of the EPRMLprocessing circuit 26. The switching control signal SW operates toreplace demodulation data of the fixed period by demodulation data ofthe EPRML processing circuit 26.

[0084] Even with the construction of the PRML processing circuit otherthan those shown in the foregoing embodiments, a data reliability can begenerated easily by the above-mentioned method.

[0085] Next, an embodiment of the EPRML processing circuit 26 will beshown in FIG. 12 and the construction thereof will be described. TheEPRML processing circuit 26 is composed of a branch metric generatingsection 30, an ACS circuit 31 and a path memory 32 and has a circuitconstruction based on the EPRML trellis diagram shown in FIG. 2B. Thebranch metric generating section 30 provides the branch metric of astate transition generated from each state of the EPRML trellis diagram.The ACS 31 performs the addition of path metrics BM0(k-1) to BM7(k-1) ofeight states and branch metric values at a present instant of time,comparison and selection to generate a path metric value for a pathhaving the highest probability. The path memory 32 performs thegeneration of decode data on the basis of the result of comparison foreach state. In order to control the whole of the EPRML processingcircuit 26 by an EPRML activation signal EPRON, the initial values ofpath metrics PM0to PM7 are controlled. After the generation of an EPRMLactivation signal EPRON pulse, the initial values of path metricsBM0(k-1) to BM7(k-1) are given by a path metric initializing circuit 33.The path metric initializing circuit 33 makes only one of eight resetsignals active on the basis of PRML demodulation data corresponding tothe timing of generation of the EPRML activation signal. This resetsignal is a path metric initializing signal which makes only one of thepath metric values of eight states smaller than the other path metricvalues. With this reset signal, a path metric value at the time ofactivation of the EPRML processing circuit is started from one of theeight states having the highest probability and the subsequent datademodulation becomes possible with the matchability in data demodulationwith the PRML processing circuit being kept.

[0086] A path metric initializing method for EPRML processing circuitother than the construction in the above-mentioned embodiment includes amethod in which the path metric value is initialized by an EPRML receivesignal. This can be realized by removing the path metric initializingcircuit 33 shown in FIG. 12 and merely connecting the EPRML activationsignal to a path metric value initializing signal of each state, whichwill has no need of illustration. With this construction, the pathmetric values of the respective states are all initialized as the samevalue and the path metric value of each state at the time of input of anEPRML activation signal is determined by an EPRML receive signal beforethe EPRML activation signal is inputted. In the case of the (0, 4/4)code, this is realized by increasing the delay time of the delay circuit23 (see FIG. 1) by 10 samples. According to the path metric initializingmethod in the present embodiment, the path metric initializing circuitcan be simplified with the realization of reduction in circuit scale andreduction in power consumption but an EPRML receive signal of 2(h+1)samples at the maximum in the case of (0, m/h) code is required prior tothe EPRML activation signal. This means an increase in delay time of thedelay circuit 23. As a result, the circuit scale and the powerconsumption of the delay circuit 23 are increased. Accordingly, thecircuit scale and the power consumption of the whole of the datademodulating circuit are determined by the reduction in circuit scale ofthe initializing circuit and the increase in delay time of the delaycircuit, that is, by coding.

[0087] Next, an embodiment of giving a data reliability on the basis ofdemodulation data which does not exist in (or match with) a coding rulewill be shown in FIG. 13 and the construction thereof will be described.The basic construction of the present embodiment is a construction inwhich a mis-code detecting circuit 35 is added to the data demodulatingcircuit shown in FIG. 1. The mis-code detecting circuit 35 performs thecomparison with a code table on the basis of demodulation data of a PRMLprocessing circuit 22 or performs a so-called decoding process and turnsa mis-code detection signal on in the case where a data series existingin no code table is detected. EPRML activation signal EPRON turn-onconditions of a data reliability information detecting circuit 24include the mis-code detection signal in addition to reliabilityinformation of the likelihood differences of two states of the PRMLprocessing circuit 22 and the detection of a path memory overflow.

[0088] In the case where mis-code is detected by the mis-code detectingcircuit 35, an EPRML processing circuit 26 performs the demodulation ofdata on the basis of an EPRML receive signal in a period of timeindicated by the EPRML activation signal. Further, a multiplexer 28performs a processing for replacement of demodulation data of the PRMLprocessing circuit 22 by demodulation data of the EPRML processingcircuit 26 corresponding thereto. As shown in the foregoing, theabove-mentioned data demodulating circuit can also be constructed byusing the coding rule as the data reliability.

[0089]FIG. 14 shows another embodiment of the data demodulating circuitof the present invention. Demodulation data generated from a datademodulator 1.1 and reliability information for the demodulation dataare supplied to a plurality of data demodulators 1.2, 1.3 and 1.4 in thenext stage to control the operations of these demodulators by datareliability information having different thresholds for datareliability. The outputs of the data demodulators 1.2, 1.3 and 1.4 areselected by a multiplexer 28 at any time. With such a construction, itbecomes possible to use a high-efficiency data demodulator with largecircuit scale and power consumption more properly in accordance with itscapability. The number of data demodulators in the next stage can be setarbitrarily. Also, the reliability information is generated on the basisof a likelihood difference. The data discriminating capabilities of thedata demodulators may be different, the same or partially different.

[0090]FIG. 15 shows a further embodiment of the data demodulatingcircuit of the present invention. Data demodulators 1.1, 1.2 and 1.3have different data discriminating capabilities and each datademodulator outputs demodulation data and reliability information forthe demodulation data. Each of multiplexers 36 and 28 receives a datademodulator selection signal provided by a decision circuit 37 to selectand output one corresponding information. The multiplexer 36 selects thecorresponding reliability information and outputs it to the decisioncircuit 37. The multiplexer 28 selects demodulation data of thecorresponding data demodulator and outputs it as demodulation data ofthe demodulating circuit. The decision circuit 37 decides a receivesignal demodulating performance on the basis of reliability informationof a data demodulator which is being used at the present time. Forexample, in the case where the data demodulator 1.1 is being used, thereliability information of the data demodulator 1.1 is transmitted tothe decision circuit 37 through the multiplexer 36. In the case where itis decided that the reliability information is remarkably deteriorated,the decision circuit 37 performs data demodulation using a datademodulator having a higher data demodulating or discriminatingcapability. For example, the data demodulator 1.2 is selected to performa data demodulation processing. The decision circuit 37 may be adedicated hardware or a software controlled by a microcomputer. In thecase where the control is made by the software, an example of theconstruction of reliability information as the output of the multiplexer36 and selection information for the multiplexers 36 and 28 may be givenin a register whose information can be controlled by the software.According to the present embodiment, an effect similar to those in theforegoing embodiments can be obtained and it becomes possible to use adata demodulator with high data discriminating capability but with largepower consumption because of its complicated circuit construction moreproperly in accordance with its capability. The number of datademodulators can be set arbitrarily. The reliability information isgenerated on the basis of a likelihood difference.

[0091]FIG. 16 shows an embodiment of a magnetic recording/reproducingapparatus using the data demodulating circuit of the present invention.The communication of data between an external device such as a personalcomputer and the magnetic recording/ reproducing apparatus is performedthrough a controller 102 in the magnetic recording/reproducingapparatus. First, explanation will be made of the case where data fromthe external device is to be recorded. When a data recording instructionis received, an instruction for movement of a recording/reproducing head106 to a position (or track) to be subjected to recording is issued fromthe controller 102 to a servo control circuit 103. After the completionof movement of the recording/ reproducing head, recording data isrecorded onto a recording medium 107 through a recording data processingcircuit 104, an R/W amplifier 105 and the recording/ reproducing head106.

[0092] The recording data processing circuit 104 is composed of anencoder 111, a synthesizer 112, a precoder 113 and a recordingcorrection circuit 114. The encoder 111 subjects recording data to acoding process following a coding rule, for example, 8/9GCR (0, 4/4)code conversion. The encoded data series is delivered in accordance witha recording bit period of the synthesizer 112. The precoder 113 makesthe code conversion of the data series again in order to give a fixedrestraint condition to the data series. The recording correction circuit114 removes the non-linearity of a recording process peculiar tomagnetic recording. The recording process is performed through the aboveoperation.

[0093] Next, a data reproducing operation will be described. When a datareproducing instruction is received, an instruction for movement of therecording/ reproducing head 106 to a data-recorded position (or track)is issued from the controller 102 to the servo control circuit 103.After the completion of movement of the recording/reproducing head, asignal recorded on the recording medium 107 is inputted to a datademodulating circuit 108 through the recording/reproducing head 106 andthe R/W amplifier 105. Demodulation data demodulated by the datademodulating circuit 108 is outputted to the controller 102 which inturn transfers the data to the external device after checking thevalidity of data.

[0094] The data demodulating circuit 108 is composed of an AGC circuit121 for making the amplitude of a reproduced waveform from the headconstant, a band elimination filter (LPF) 122 for eliminating noisesoutside of a signal band, an AD converter 123 for sampling thereproduced signal, an equalizer (EQ) 124 for eliminating interferencebetween codes from the reproduced waveform, a phase synchronizing (orPLL) circuit 125 for determining the timing of sampling by the ADconverter 123, a data demodulating circuit 1 according to the presentinvention, and a decoder 127 for performing a process for decoding ofdemodulation data.

[0095] A microcomputer 101 performs a processing for the whole of theapparatus inclusive of the controller 102 and the data demodulatingcircuit 108 by software. In the shown example, the microcomputer 101performs the detection of the result of detection by a codecontravention detecting circuit 128 (which will be mentioned later on),the detection of a likelihood difference of a PRML processing circuit22, the setting of a register 21 for giving a decision threshold of adata reliability information detecting circuit 24, and so forth.

[0096] Basically, the data demodulating circuit 1 can be constructed bythe data demodulating circuit in all the data demodulating circuits ofthe foregoing embodiments and the operation is the same as thatmentioned in the foregoing. The code contravention detecting circuit 128in the present embodiment detects the input of demodulation data havingno matching with the coding rule when the process for decoding ofdemodulation data is performed by the decoder 127. An output of the codecontravention detecting circuit 128 is delivered to a register 21 or asin interruption signal to the microcomputer 101.

[0097] In the present embodiment, there is shown a construction in whichthe likelihood differences of two states of a PRML processing circuit 22are detectable by the microcomputer 101. The microcomputer 101 may usethe code contravention detecting circuit or the likelihood differencesof two states of the PRML processing circuit 22 to perform a processingwhich include, for example, the change of a setting value of theregister 21 for changing a decision threshold of a data reliabilityinformation detecting circuit 24 or the switching in process to a datademodulating circuit (not shown) having a higher data demodulatingcapability. Further, it is also possible to change the data demodulatingcapability by utilizing those reliability information to change thefilter coefficients of the LPF 122 and the equalizer 124 or the variouscharacteristics of the AGC 121 and the PLL 125. According to theembodiment mentioned above, a magnetic recording/reproducing apparatushaving a high data demodulating capability in spite of a low powerconsumption is constructed. Also, the power consumption of arecording/reproducing control LSI formed by the LSI configuration of therecording data processing circuit 104 and the data demodulating circuit108 can be made low by using the present invention.

[0098] In the present invention, the PRML and EPRML processing circuits22 and 23 are disclosed as the first and second data demodulators,respectively. However, the kinds of the first and second datademodulators are not limited to the disclosed examples.

[0099] So far as a relationship between the data discriminatingcapability of the first data demodulator and the data discriminatingcapability of the second data demodulator have a relationship is suchthat the latter is higher than the former, any combination of two of aPRML data demodulator, an EPRML data demodulator, an EEPRM datademodulator and TRELLIS data demodulator is possible. If the aboverelationship is satisfied, other data demodulators may be used.

[0100] The present invention is not limited to the disclosed embodimentsand includes any modifications which are included by the spirit ofclaims.

1. An information recording/reproducing method in an informationrecording/reproducing apparatus including a plurality of datademodulators which perform the data demodulation of an input signal, themethod comprising: a step of generating operation control informationfrom at least one of reliability information for error informationand/or demodulation data generated by a first data demodulator which isone of said plurality of data demodulators; and a step of controllingthe operation of a second data demodulator on the basis of saidoperation control information, said second data demodulator being one ofsaid plurality of data demodulators other than said first datademodulator.
 2. An information recording/reproducing method according toclaim 1 , wherein the step of generating said operation controlinformation includes a step of generating said operation controlinformation on the basis of a likelihood difference at the time of datademodulation.
 3. An information recording/reproducing method accordingto claim 1 , wherein the step of generating said operation controlinformation includes a step of generating said operation controlinformation on the basis of a plurality of survival paths which exist ina predetermined time.
 4. An information recording/reproducing methodaccording to claim 1 , wherein the step of generating said operationcontrol information includes a step of generating said operation controlinformation on the basis of a predetermined value of the run length ofsaid demodulation data.
 5. An information recording/reproducing methodaccording to claim 1 , wherein the step of generating said operationcontrol information includes a step of generating said operation controlinformation on the basis of whether or not the result of codedemodulation performed on the basis of said demodulation data matcheswith a predetermined code.
 6. An information recording/reproducingmethod according to claim 1 , further comprising a step of replacingdemodulation data of said first data demodulator by demodulation data ofsaid second data demodulator on the basis of said operation controlinformation.
 7. An information recording/reproducing method according toclaim 1 , further comprising a step of replacing demodulation data ofsaid first data demodulator by demodulation data of said second datademodulator for a data decision period from the instant of time ofgeneration of a plurality of survival paths of said first datademodulator to an instant of time when one survival path is selectedagain, the replacement being performed on the basis of the reliabilityinformation of demodulation data generated in said data decision period.8. An information recording/reproducing method according to claim 1 ,wherein the step of controlling the operation of said second datademodulator includes a step of setting an initial state of said seconddata demodulator on the basis of said operation control information. 9.An information recording/reproducing method according to claim 1 ,wherein the step of controlling the operation of said second datademodulator includes a step of setting an initial state of said seconddata demodulator by use of demodulation data generated by said firstdata demodulator before the generation of said reliability information.10. An information recording/reproducing method according to claim 1 ,further comprising a step of converting said input signal into a signaladapted for data demodulation by said second data demodulator.
 11. Aninformation recording/reproducing method in an informationrecording/reproducing apparatus including a plurality of datademodulators which have different data discriminating capabilities foran input signal, the method comprising: a step of generating operationcontrol information from at least one of reliability information forerror information and/or demodulation data generated by a first datademodulator of said plurality of data demodulators which has a lowerdata discriminating capability; and a step of controlling the operationof a second data demodulator on the basis of said operation controlinformation, said second data demodulator being one of said plurality ofdata demodulators which has a higher data discriminating capability. 12.An information recording/reproducing method according to claim 11 ,wherein the step of generating said operation control informationincludes a step of generating said operation control information on thebasis of a likelihood difference at the time of data demodulation. 13.An information recording/reproducing method according to claim 11 ,wherein the step of generating said operation control informationincludes a step of generating said operation control information on thebasis of a plurality of survival paths which exist in a predeterminedtime.
 14. An information recording/reproducing method according to claim11 , wherein the step of generating said operation control informationincludes a step of generating said operation control information on thebasis of a predetermined value of the run length of said demodulationdata.
 15. An information recording/reproducing method according to claim11 , wherein the step of generating said operation control informationincludes a step of generating said operation control information on thebasis of whether or not the result of code demodulation performed on thebasis of said demodulation data matches with a predetermined code. 16.An information recording/reproducing method according to claim 11 ,further comprising a step of replacing demodulation data of said firstdata demodulator by demodulation data of said second data demodulator onthe basis of said operation control information.
 17. An informationrecording/reproducing method according to claim 11 , further comprisinga step of replacing demodulation data of said first data demodulator bydemodulation data of said second data demodulator for a data decisionperiod from the instant of time of generation of a plurality of survivalpaths of said first data demodulator to an instant of time when onesurvival path is selected again, the replacement being performed on thebasis of the reliability information of demodulation data generated insaid data decision period.
 18. An information recording/reproducingmethod according to claim 11 , wherein the step of controlling theoperation of said second data demodulator includes a step of setting aninitial state of said second data demodulator on the basis of saidoperation control information.
 19. An information recording/reproducingmethod according to claim 11 , wherein the step of controlling theoperation of said second data demodulator includes a step of setting aninitial state of said second data demodulator by use of demodulationdata generated by said first data demodulator before the generation ofsaid reliability information.
 20. An information recording/reproducingmethod according to claim 11 , further comprising a step of convertingsaid input signal into a signal adapted for data demodulation by saidsecond data demodulator.
 21. An information recording/reproducing methodin an information recording/reproducing apparatus including a pluralityof data demodulators which perform the data demodulation of an inputsignal, the method comprising: a step of generating first demodulationdata and reliability information of said first demodulation data by adata demodulator in a first stage of said plurality of datademodulators; a step of supplying said first demodulation data and saidreliability information of said first demodulation data to the datademodulators in the next stage; a step of controlling the operations ofthe data demodulators in said next stage on the basis of controlinformation having different thresholds for said reliability informationof said first demodulation data; and a step of selecting seconddemodulation data from the data demodulators in said next stage.
 22. Aninformation recording/reproducing method according to claim 21 , whereinthe step of generating said reliability information includes a step ofgenerating said reliability information on the basis of a likelihooddifference at the time of data demodulation.
 23. An informationrecording/reproducing method in an information recording/reproducingapparatus including a plurality of data demodulators which perform thedata demodulation of an input signal, the method comprising: a step ofsupplying said input signal to said plurality of data demodulators, saidplurality of data demodulators having different data discriminatingcapabilities; a step of deciding a demodulation performance fromreliability information for demodulation data generated by a first datademodulator which is one of said plurality of data demodulators; a stepof controlling the operations of the others of said plurality of datademodulators on the basis of the result of decision; and a step ofselecting outputs of said plurality of data demodulators on the basis ofsaid result of decision.
 24. An information recording/reproducing methodaccording to claim 23 , wherein said reliability information isgenerated on the basis of a likelihood difference at the time of datademodulation.
 25. An information recording/reproducing apparatuscomprising: a plurality of data demodulators each of which performs thedata demodulation of an input signal; means for generating operationcontrol information from at least one of reliability information forerror information and/or demodulation data generated by a first datademodulator which is any one of said plurality of data demodulators; andmeans for controlling the operation of a second data demodulator on thebasis of said operation control information, said second datademodulator being one of said plurality of data demodulators other thansaid first data demodulator.
 26. An information recording/reproducingapparatus according to claim 25 , wherein the means for generating saidoperation control information includes means for generating saidoperation control information on the basis of a likelihood difference atthe time of data demodulation.
 27. An information recording/reproducingapparatus according to claim 25 , wherein the means for generating saidoperation control information includes means for generating saidoperation control information on the basis of a plurality of survivalpaths which exist in a predetermined time.
 28. An informationrecording/reproducing apparatus according to claim 25 , wherein themeans for generating said operation control information includes meansfor generating said operation control information on the basis of apredetermined value of the run length of said demodulation data.
 29. Aninformation recording/reproducing apparatus according to claim 25 ,wherein the means for generating said operation control informationincludes means for generating said operation control information on thebasis of whether or not the result of code demodulation performed on thebasis of said demodulation data matches with a predetermined code. 30.An information recording/reproducing apparatus according to claim 25 ,further comprising means for replacing demodulation data of said firstdata demodulator by demodulation data of said second data demodulator onthe basis of said operation control information.
 31. An informationrecording/reproducing apparatus according to claim 25 , furthercomprising means for replacing demodulation data of said first datademodulator by demodulation data of said second data demodulator for adata decision period from the instant of time of generation of aplurality of survival paths of said first data demodulator to an instantof time when one survival path is selected again, the replacement beingperformed on the basis of the reliability information of demodulationdata generated in said data decision period.
 32. An informationrecording/reproducing apparatus according to claim 25 , wherein themeans for controlling the operation of said second data demodulatorincludes means for setting an initial state of said second datademodulator on the basis of said operation control information.
 33. Aninformation recording/reproducing apparatus according to claim 25 ,wherein the means for controlling the operation of said second datademodulator includes means for setting an initial state of said seconddata demodulator by use of demodulation data generated by said firstdata demodulator before the generation of said reliability information.34. An information recording/reproducing apparatus according to claim 25, further comprising means for controlling from the exterior a decisionrange of the reliability information of the demodulation data generatedby said first data demodulator.
 35. An information recording/reproducingapparatus according to claim 25 , wherein the means for controlling saiddecision range from the exterior includes a register for setting saiddecision range.
 36. An information recording/reproducing apparatusaccording to claim 25 , further comprising means for converting saidinput signal into a signal adapted for data demodulation by said seconddata demodulator.
 37. An information recording/reproducing apparatusaccording to claim 25 , wherein the combination of said first and seconddata demodulators includes any combination of a PRML data demodulator,an EPRML data demodulator, an EEPRML data demodulator and a TRELLIS datademodulator.
 38. An information recording/reproducing apparatuscomprising: a plurality of data demodulators which perform the datademodulation of an input signal and have different data discriminatingcapabilities; means for generating operation control information from atleast one of reliability information for error information and/ordemodulation data generated by a first data demodulator of saidplurality of data demodulators which has a lower data discriminatingcapability; and means for controlling the operation of a second datademodulator on the basis of said operation control information, saidsecond data demodulator being one of said plurality of data demodulatorswhich has a data discriminating capability higher than that of saidfirst data demodulator.
 39. An information recording/reproducingapparatus according to claim 38 , wherein the means for generating saidoperation control information includes means for generating saidoperation control information on the basis of a likelihood difference atthe time of data demodulation.
 40. An information recording/reproducingapparatus according to claim 38 , wherein the means for generating saidoperation control information includes means for generating saidoperation control information on the basis of a plurality of survivalpaths which exist in a predetermined time.
 41. An informationrecording/reproducing apparatus according to claim 38 , wherein themeans for generating said operation control information includes meansfor generating said operation control information on the basis of apredetermined value of the run length of said demodulation data.
 42. Aninformation recording/reproducing apparatus according to claim 38 ,wherein the means for generating said operation control informationincludes means for generating said operation control information on thebasis of whether or not the result of code demodulation performed on thebasis of said demodulation data matches with a predetermined code. 43.An information recording/reproducing apparatus according to claim 38 ,further comprising means for replacing demodulation data of said firstdata demodulator by demodulation data of said second data demodulator onthe basis of said operation control information.
 44. An informationrecording/reproducing apparatus according to claim 38 , furthercomprising means for replacing demodulation data of said first datademodulator by demodulation data of said second data demodulator for adata decision period from the instant of time of generation of aplurality of survival paths of said first data demodulator to an instantof time when one survival path is selected again, the replacement beingperformed on the basis of the reliability information of demodulationdata generated in said data decision period.
 45. An informationrecording/reproducing apparatus according to claim 38 , wherein themeans for controlling the operation of said second data demodulatorincludes means for setting an initial state of said second datademodulator on the basis of said operation control information.
 46. Aninformation recording/reproducing apparatus according to claim 38 ,wherein the means for controlling the operation of said second datademodulator includes means for setting an initial state of said seconddata demodulator by use of demodulation data generated by said firstdata demodulator before the generation of said reliability information.47. An information recording/reproducing apparatus according to claim 38, further comprising means for controlling from the exterior a decisionrange of the reliability information of the demodulation data generatedby said first data demodulator.
 48. An information recording/reproducingapparatus according to claim 38 , wherein the means for controlling saiddecision range from the exterior includes a register for setting saiddecision range.
 49. An information recording/reproducing apparatusaccording to claim 38 , further comprising means for converting saidinput signal into a signal adapted for data demodulation by said seconddata demodulator.
 50. An information recording/reproducing apparatusaccording to claim 38 , wherein the combination of said first and seconddata demodulators includes any combination of a PRML data demodulator,an EPRML data demodulator, an EEPRML data demodulator and a TRELLIS datademodulator.
 51. An information recording/reproducing apparatuscomprising: first and second data demodulators which perform the datademodulation of an input signal with different data discriminatingcapabilities, respectively, the data discriminating capability of saidfirst data demodulator being lower than that of said second datademodulator; a control circuit connected between said first and seconddata demodulators for controlling the operation of said second datademodulator on the basis of reliability information of error informationand/or demodulation data generated by said first data demodulator; and acircuit for synthesizing demodulation data of said first and second datademodulators.
 52. An information recording/reproducing apparatusaccording to claim 51 , wherein said control circuit includes a circuitfor generating a control signal on the basis of a likelihood differenceat the time of data demodulation.
 53. An informationrecording/reproducing apparatus according to claim 51 , wherein saidcontrol circuit includes a circuit for generating a control signal onthe basis of a plurality of survival paths which exist in apredetermined time.
 54. An information recording/reproducing apparatusaccording to claim 51 , wherein said control circuit includes a circuitfor generating a control signal on the basis of a predetermined value ofthe run length of said demodulation data.
 55. An informationrecording/reproducing apparatus according to claim 51 , furthercomprising a mis-code detecting circuit between said first datademodulator and said control circuit, said control circuit including acircuit for generating a control signal on the basis of an output ofsaid mis-code detecting circuit.
 56. An informationrecording/reproducing apparatus according to claim 51 , wherein saidcircuit for synthesizing the demodulation data includes a multiplexerfor synthesizing the demodulation data of said first and second datamodulators in accordance with a control signal from said controlcircuit.
 57. An information recording/reproducing apparatus according toclaim 51 , wherein said control circuit includes a circuit fordetermining a data decision period from the instant of time ofgeneration of a plurality of survival paths of said first datademodulator to an instant of time when one survival path is selectedagain, and a circuit for replacing demodulation data of said first datademodulator by demodulation data of said second data demodulator on thebasis of the reliability information of demodulation data generated insaid data decision period.
 58. An information recording/reproducingapparatus according to claim 51 , wherein said control circuit includesa circuit for setting an initial state of said second data demodulatoron the basis of said reliability information of the error informationand/or the demodulation data.
 59. An information recording/reproducingapparatus according to claim 51 , wherein said control circuit includesa circuit for setting an initial state of said second data demodulatorby use of demodulation data generated by said first data demodulatorbefore the generation of said reliability information.
 60. Aninformation recording/reproducing apparatus according to claim 51 ,further comprising a register connected to said control circuit forsetting a decision range of said reliability information of thedemodulation data.
 61. An information recording/reproducing apparatusaccording to claim 51 , further comprising a signal conversion circuitfor converting said input signal into a signal adapted for said seconddata demodulator.
 62. An information recording/reproducing apparatusaccording to claim 51 , further comprising a delay circuit for delayingsaid input signal to supply the delayed input signal to said second datademodulator.
 63. An information recording/reproducing apparatusaccording to claim 51 , further comprising a delay circuit for delayingdemodulation data of said first demodulator.
 64. An informationrecording/reproducing apparatus according to claim 51 , wherein thecombination of said first and second data demodulators includes anycombination of a PRML data demodulator, an EPRML data demodulator, anEEPRML data demodulator and a TRELLIS data demodulator.
 65. Aninformation recording/reproducing apparatus comprising: a first datademodulator for receiving an input signal to generate demodulation dataand reliability information of the demodulation data; a plurality ofsecond data demodulators connected to the rear stage of said first datademodulator for receiving said demodulation data and said reliabilityinformation of the demodulation data; and a circuit for synthesizingdemodulation data of said plurality of second data demodulators.
 66. Aninformation recording/reproducing apparatus according to claim 65 ,wherein said plurality of second data demodulators include circuits fordeciding said reliability information by different thresholds,respectively.
 67. An information recording/reproducing apparatuscomprising: a plurality of data demodulators which have different datadiscriminating capabilities and receive the same input signal; a firstmultiplexer connected to said plurality of data demodulators forselecting reliability information for demodulation data respectivelygenerated by said data demodulators; a decision circuit connected tosaid first multiplexer for deciding the demodulation performance of aselected data demodulator; and a second multiplexer connected to saidplurality of data demodulators for selecting demodulation data from saidplurality of data demodulators in accordance with a signal from saiddecision circuit.
 68. An information recording/reproducing apparatusaccording to claim 67 , wherein said decision circuit includes a circuitfor deciding the demodulation performance on the basis of a likelihooddifference at the time of data demodulation.
 69. An informationrecording/reproducing apparatus comprising: a first data demodulatorwhich performs the data demodulation of an input signal; a second datademodulator which has a data discriminating capability higher than thatof said first data demodulator and performs the data demodulation ofsaid input signal; a control circuit for deciding a reliability fordemodulation data generated by said first data demodulator to operatesaid second data demodulator having the higher data discriminatingcapability when said reliability is deteriorated; and a circuit forreplacing demodulation data of said first data demodulator bydemodulation data of said second data demodulator during a period oftime when said reliability is deteriorated.
 70. An informationrecording/reproducing apparatus according to claim 69 , wherein saidcontrol circuit includes a circuit for deciding said reliability on thebasis of a likelihood difference.
 71. An informationrecording/reproducing apparatus according to claim 69 , wherein saidcontrol circuit includes a circuit for deciding said reliability on thebasis of a run length of the demodulation data.
 72. An informationrecording/reproducing apparatus according to claim 69 , wherein saidcontrol circuit includes a circuit for deciding said reliability on thebasis of whether or not the demodulation data exists in a predeterminedcode.
 73. An information recording/reproducing apparatus according toclaim 69 , wherein said control circuit includes a circuit for decidingsaid reliability on the basis of error information of the demodulationdata.
 74. An information recording/reproducing apparatus according toclaim 69 , wherein said first data demodulator has a power consumptionsmaller than that of said second data demodulator.
 75. An informationrecording/reproducing apparatus comprising: a first data demodulatorwhich performs the data demodulation of an input signal; a second datademodulator which performs the data demodulation of said input signalwith a power consumption larger than that of said first datademodulator; a control circuit for deciding a reliability fordemodulation data generated by said first data demodulator to operatesaid second data demodulator when said reliability is deteriorated; anda circuit for replacing demodulation data of said first data demodulatorby demodulation data of said second data demodulator during a period oftime when said reliability is deteriorated.
 76. An informationrecording/reproducing apparatus according to claim 75 , wherein saidcontrol circuit includes a circuit for deciding said reliability on thebasis of a likelihood difference.
 77. An informationrecording/reproducing apparatus according to claim 75 , wherein saidcontrol circuit includes a circuit for deciding said reliability on thebasis of a run length of the demodulation data.
 78. An informationrecording/reproducing apparatus according to claim 75 , wherein saidcontrol circuit includes a circuit for deciding said reliability on thebasis of whether or not the demodulation data exists in a predeterminedcode.
 79. An information recording/reproducing apparatus according toclaim 75 , wherein said control circuit includes a circuit for decidingsaid reliability on the basis of error information of the demodulationdata.
 80. An information recording/reproducing apparatus according toclaim 75 , where said second data demodulator has a data discriminatingcapability higher than that of said first data demodulator.